The present invention relates to an input/output paging mechanism in a data processor using a virtual memory.
The virtual memory permits the user to treat secondary storage as an extension of a main memory unit, thus giving the performance of a larger main memory.
A conventional construction of a data processor using a virtual memory is shown in FIG. 1.
In FIG. 1, a system control processor (SCP) 11, a main memory unit (MMU) 13 and input/output processors (IOP) 17, 18 are connected to a system bus 15. Further, a magnetic disk unit (MK) 19 and a floppy disk unit 20 are connected to the IOPs 17, 18, respectively. The system bus 15 comprises address, data and control lines. In particular, the control lines comprise 32 lines to be able to specify virtual addresses up to 4 giga bytes (GB)=4.times.10.sup.9 bytes.
The SCP 11 controls the individual units connected to the system bus 15 under control of a program stored in the MMU 13 in which various programs and data are stored including channel programs and address translating tables (page tables) for the use of a list service and a data service. The list service defines the operation for accessing a channel command entry list (CCE list), and the data service defines the operation of a data transfer.
The IOPs 17 and 18 control the data flow between the I/O devices 19, 20 and the MMU 13. Thus, the release of the SCP 11 from the I/O processing permits the parallel operation of the SCP processing and the I/O processing. The I/O processing is carried out with a start I/O (SIO) instruction and a channel program. The SIO instruction includes an address specifying a start address of the channel program, a channel number and the I/O device number to be controlled. The execution of the SIO instruction by the SCP 11 triggers the IOP 17 to control the I/O operation. The channel program comprises the CCE list and a channel program header (CPH). The CCE list consists of a series of channel commands. The CPH includes a start address of the CCE list, completion status, the number of real data transfer bytes, completion CCE address and so on.
The channel program is stored in the MMU 13. The address space of the MMU 13 is 16 mega bytes (MB), for example, and is divided into physical blocks of words called pages, each having 4KB.
There are two types of addressing modes: a physical addressing mode and a logical addressing mode, as shown in FIGS. 2A and 2B. In the physical addressing mode, a physical address within an effective address space of the MMU 13 is specified in a displacement field of bits 0 through 31, for example. In the logical addressing mode, a logical page number which specifies the page in the virtual address space is specified in bits 8 to 19, and the relative address within the page is specified in bits 20 to 31 of the displacement field, for example.
When the SIO instruction is executed by the SCP 11, the specified IOP reads the CPH to obtain the start address of the CCE list. Then, the IOP 17 reads the corresponding CCE list based on the obtained start address. The IOP decodes and executes each CCE independently of the processing by the SCP 11. Executing the final CCE, the IOP 17 informs the SCP 11 of the termination of the data transfer using an interrupt function.
However, in the prior art system, a virtual address specified in the SIO instruction should be translated into an effective address by a software means such as an operating system (OS) under the control of the SCP 11. Thus, the increase of the overhead operations for the address translation degrades the system performance.
To eliminate the above drawbacks, an IOP having an address translating mechanism functioning as an input and output paging mechanism (I/O paging mechanism) has been developed. In this prior art system, a page table for holding the logical addresses specifying the CCEs is provided in the MMU 13. Further, a page table pointer (PTP1) specifying the page table is stored in the CPH. When the SIO instruction is executed by the SCP 11, the specified IOP reads the CPH to obtain a page table pointer (PTP) which specifies the start address of a page table (PT). Then, the IOP 17 reads the PT and obtains a PT word from the location specified by one part of a channel command entry pointer (CCEP). Then, the IOP 17 reads the CCE list and obtains the address of a data transfer area, data transfer size and so on from the locations specified by the PT word and another part of the CCEP. However, a page table for logically specifying a data transfer area is not provided in the MMU 13. Therefore, there is a severe restriction in that the data transfer area should be within a continuous space specified by the CCE. That is, the CCE list cannot be set over multiple pages. In such a situation, an OS designer must always keep in mind the locations of the data transfer area in a physical address mode.